In portable digital devices, such as digital cellular telephones, and any other digital applications which are sensitive to power consumption or power dissipation, such as picocell cellular base stations, reducing, power consumption is an important consideration. In portable devices powered by a battery for example, reducing power consumption can extend the period of time in which the portable device is operable, before the battery requires replacing or recharging. Even with non-battery powered devices, there is an advantage in reducing power dissipation in that it can improve reliability of the components of the device.
Digital circuits, which are part of a digital device, such as a digital cellular telephone, require as inputs a supply voltage Vdd and a clock signal. Power consumption (P) in such a digital circuit can be approximated by the following equation: EQU P=c*Fref*Vdd.sup.2
where
Fref is the frequency of the clock signal which clocks the digital circuit PA1 c is the equivalent capacitance of the digital circuit PA1 Vdd is the supply voltage of the digital circuit PA1 determining a propagation delay of a signal along a signal path in the digital circuit, the signal being clocked along the signal path by a clock signal, and the determining step comprising the steps of: PA1 adjusting the level of the supply voltage in dependence on the phase error signal until the propagation delay is determined to reach a predetermined period when the phase error signal is zero, the supply voltage having a first level when the determined propagation delay reaches the predetermined period; and PA1 providing the supply voltage having the first level to components of the digital circuit. PA1 determining a task to be performed by the digital circuit; PA1 adjusting the frequency of the clock signal in dependence on the determined task and supplying the adjusted clock signal to components of the digital circuit; PA1 determining a propagation delay of a signal along a signal path in the digital circuit, the signal being clocked along the signal path by a clock signal, and the determining step comprising the steps of: PA1 adjusting the level of the supply voltage to provide an adjusted supply voltage in dependence on the adjusted frequency of the clock signal and on the phase error signal until the determined propagation delay reaches a predetermined period when the phase error signal is zero, the supply voltage having a first level when the determined propagation delay reaches the predetermined period; and PA1 providing the supply voltage having the first level to components of the digital circuit.
Thus, from this equation it is clear that by reducing the clock frequency Fref and the supply voltage Vdd, but only to the limit that ensures proper function of the digital circuit, power consumption can be reduced.
A number of different methods for reducing power consumption have already been contemplated. For example, it is known for some applications to run the clock signal as fast as possible when processing is required and then when no processing is required, completely stopping the clock. This method could not be used in applications requiring some processing substantially all of the time. U.S. Pat. No. 5,378,935 discloses a method for optimising power consumption by adjusting the clock frequency of the clock signal according to the need for processing power. Both these methods achieve a linear decrease in power consumption.
Similarly it is also known to achieve a reduction in power consumption by running at a constant lower supply voltage. Since power consumption depends on Vdd.sup.2, such a reduction in the supply voltage achieves increased power savings. However, this may result in poorer performance which may be unacceptable in some applications.
Some known systems reduce power consumption by having a power down mode during which the supply voltage is zero. As with those systems which have periods in which the clock is completely stopped, this technique cannot be used in applications requiring some processing substantially all the time.
Japanese patent application no. JP 08 136621 describes a power supply voltage supplying device which adjusts the voltage supplied to a device by comparing the delay of a pulse through a delay circuit with a predetermined value.
PCT patent application no. WO 90 13079 describes a computing system with selective operating voltage. The system determines the minimum voltage that can be used to ensure proper operation of elements in the system for different bus speeds and stores the determined voltage levels in a memory. In use, the voltage level is then selected using the contents of the memory according to the bus speed.
European patent application no. EP-A-0722137 discloses a clock control system for dynamically varying the internal clock frequency of a microprocessor.
U.S. Pat. No. 4,691,124 describes a self-compensating maximum speed integrated circuit. A clock is generated according to a slowest signal path of the integrated circuit.
European Patent Application EP-A-0632360 describes a method for reducing power consumption by adjusting the frequency of the clock signal and the supply voltage according to the task to be performed. Like all the known methods, the method disclosed in this patent application does not take account of variations in circuit parameters with time and from circuit to circuit, due to for example, temperature, aging and circuit fabrication process.
There is therefore a need for an improved method for dynamically controlling the power consumption in a digital circuit which overcomes the above referenced disadvantages.